1. Field of the Invention
The present invention relates to the field of integrated circuit design; more specifically, it relates to a method of predicting manufacturing yield of a proposed integrated circuit design.
2. Background of the Invention
In the present state of the art, accurate yield prediction for an integrated circuit design based on critical area analysis can be performed only after design of the integrated circuit design is complete, while relatively simple and inaccurate die size models are used to predict yield prior to the design being completed. As integrated circuits become increasingly more complex, it is found that the pre and post design yield predictions often do not agree. Financial considerations require a more accurate method for predicating yield and hence cost at the time a new integrated circuit is under consideration. Therefore, a method that accurately predicts yield prior to design completion is required.